math - How to use arithmetic shift & selector in verilog? -


I want to add selector and arithmetic changes together. But this code has failed to implement, the result is just a logical change.

  module multiplier (x1, x2, x1x2); Input [15: 0] x1, x2; Output [15: 0] x1x2; Assign X1x2 = x2 [13]? ($ Signed (x1)>> 4'd1): 16'B 0000000000000000; Andam Module  

Arithmetic changes are successful without the selector like this code.

  module multiplier (x1, x2, x1x2); Input [15: 0] x1, x2; Output [15: 0] x1x2; X1x2 = $ signed (x1) & gt; & Gt; & Gt; 4'd1; Endmodule  

How to use selector and arithmetic changes? Verilog will almost always be unsigned when it is an option and it is allowed to select the selector logic Verilog;

If the difference is the solution: there are pairs

  • Use two lines: wire [15: 0] x1_shift = $ sign (x1)> >> 4'd1; Assign X1x2 = x2 [13]? X1_shift: 16'b0;
  • Use crisp instead of brackets: assign
      x1x2 = x2 [13]?  $ signed (x1) >>> 4'd1 } : 16'b0;  
  • Hard coded changes:

      assign x1x2 = x2 [13]? {X1 [15], x1 [15: 1]}: 16'b 0;   

    > assign x1x2 = x2 [13]? ($ Sign (x1) >>> 4'd1): $ signed (16'b0);

  • You can also cast a shape with SystemWorld:

      assign x1x2 = x2 [13]? 16 '($ sign (x1) >>> 4'd1): 16'b0; // SV Only, Verilog No  

Working example.


Comments

Popular posts from this blog

python - Overriding the save method in Django ModelForm -

html - CSS autoheight, but fit content to height of div -

qt - How to prevent QAudioInput from automatically boosting the master volume to 100%? -