Class Object Instatiation in UVM -

In the UVM cookbook, it is written that class objects are done at an instant run time. But ahead of time, during the compilation / expansion, we may have all the details of the class.

As shown in the image below (taken from UVM Cookbook), it has been shown that the modules and interfaces instant compositions have been completed in the extension phase, but the class object is created at run time. goes.

consider this sample example Please.

  // Any .sv file inside class A; Int a; Endclass AX; Initial x = new ();  

Now there is no need to create a class while running in this case, because we have the details of other classes available in computing / extension time such as other modules or interface details.

So why in systemverilog, especially only class instantiations are done on run time?

Object build in C ++ is not done at run time.

Note: In the question, I am talking about ordinary sections and not using inheritance, in which the creation of time can be compulsory. By creation, I do not mention memory allocation, because memory for all (module, interface, class) will be allocated only during simulation. I am just referring to image.

All objects run-time

Perhaps you are run-time misleading with run-foot? Run-phase is part of a phased mechanism in UVM which allows simulation to be separated between different periods. Thus all UVM components can be synchronized from the phase.

The object is created here in the build_fase, which is part of the run-time.