c - Compare and Exchange on Android (ARM) -

The code below is an ARM implementation to compare and exchange Android:

  __ ATOMIC_INLINE__ int __bionic_cmpxchg (int32_t old_value, int32_t new_value, volatile int32_t * ptr) {int32_t prev, position; Do you know how to do this? {{__asm__ __volatile__ ("ldrex% 0, [% 3] \ n" "mov% 1, # 0 \ n" "take% 0,% 4 \ n" #ifdef __thumb2__ "this eq \ n" #if endf " "+" (* Ptr): "R" (PTR),% 1,% 5, [% 3] ":" = & amp; r "(Previous)," = & amp; "IR" (old_value), "R" (new_view): "CC"); } While (__builtin_expect (status! = 0, 0)); Return prev! = Old_value; }  

Whether Strings has set the monitor in LDX, even if the situation is not equal, and if not, how safe is it?

In addition to why we want additional this eq for thumb -2?

what Strexeq ldrex Clear the monitor set even if the condition is not equal?

No need to do this - this is the "cmp" part of cmpxchg - if the value is not expected to be loaded, then teq returns < Code> ne , nothing happens, we exit the code due to mov% 1, # 0, , return, and everyone forgets the whole point.

If the price is loaded

< / P>

To set a flag (unique monitor), it is said that no one has touched the memory since "my ldrex ". If someone writes that area, then the flag gets cleared. A strex will be successful and if it feels that the flag is still set if this flag is cleared, it means that the loaded values ​​can be changed into memory, which is the atom of operation Infringes, therefore the store fails and there is no update. In this case, we have to go back to the beginning and will have to try again from scratch - eventually, we will get the entire sequence without any interruption on which this An atom will be updated.

There is no need to worry about the unique monitor situation in any case; Any later will start with a ldrex with a specific code definition, and it will start the monitor properly at that time.

Apart from this, why do we need an extra eq for Thumb2?

Because there is no conditional execution in the thumb (except for branches), there is no bit to embed the condition code in any instruction encoding. Angus-2 was introduced as a way of making a block of 4 follow-up instructions on a particular situation (or vice versa) through global ITState. Whereas some assemblers are smart enough to automatically automate the appropriate this block while collecting the ARM code for eHards, there is nothing you can trust in portable code can do.

A well-behaved codec should be ignored by this for the ARM (but still for error), but if it does not meet the conditions of the following instructions Account), but maybe this is probably the preprocessor-ed for the benefit of the stupid compiler who estimates the length of the inline ASM block with counting of Newlines.